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<title>Heterogeneous System Architecture</title>

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Heterogeneous System Architecture

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Heterogeneous System Architecture (HSA) is a cross-vendor set of specifications that allow for the integration of <a href="Central_processing_unit" title="Central processing unit">central processing units</a> and <a href="GPU" class="mw-redirect" title="GPU">graphics processors</a> on the same bus, with shared <a href="Main_memory" class="mw-redirect" title="Main memory">memory</a> and <a href="Task_(computing)" title="Task (computing)">tasks</a>.<a href="#cite_note-1">[1]</a> The HSA is being developed by the <a href="HSA_Foundation" title="HSA Foundation">HSA Foundation</a>, which includes (among many others) <a href="Advanced_Micro_Devices" class="mw-redirect" title="Advanced Micro Devices">AMD</a> and <a href="ARM_Holdings" class="mw-redirect" title="ARM Holdings">ARM</a>. The platform's stated aim is to reduce <a href="Communication_latency" class="mw-redirect" title="Communication latency">communication latency</a> between CPUs, GPUs and other <a href="Compute_device" class="mw-redirect" title="Compute device">compute devices</a>, and make these various devices more compatible from a programmer's perspective,<a href="#cite_note-whitepaper-2">[2]</a>: 3 <a href="#cite_note-whatis-3">[3]</a> relieving the programmer of the task of planning the moving of data between devices' disjoint memories (as must currently be done with <a href="OpenCL" title="OpenCL">OpenCL</a> or <a href="CUDA" title="CUDA">CUDA</a>).<a href="#cite_note-4">[4]</a>

CUDA and OpenCL as well as most other fairly advanced programming languages can use HSA to increase their execution performance.<a href="#cite_note-5">[5]</a> <a href="Heterogeneous_computing" title="Heterogeneous computing">Heterogeneous computing</a> is widely used in <a href="MPSoC" class="mw-redirect" title="MPSoC">system-on-chip</a> devices such as <a href="Tablet_computer" title="Tablet computer">tablets</a>, <a href="Smartphone" title="Smartphone">smartphones</a>, other mobile devices, and <a href="Video_game_console" title="Video game console">video game consoles</a>.<a href="#cite_note-gpuscience-6">[6]</a> HSA allows programs to use the graphics processor for <a href="Floating_point" class="mw-redirect" title="Floating point">floating point</a> calculations without separate memory or scheduling.<a href="#cite_note-7">[7]</a>

<div class="mw-heading mw-heading2"><h2 id="Rationale">Rationale</h2></div>

The rationale behind HSA is to ease the burden on programmers when offloading calculations to the GPU. Originally driven solely by AMD and called the FSA, the idea was extended to encompass processing units other than GPUs, such as other manufacturers' <a href="Digital_signal_processor" title="Digital signal processor">DSPs</a>, as well.

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<div class="gallerytext">Steps performed when offloading calculations to the <a href="Graphics_processing_unit" title="Graphics processing unit">GPU</a> on a non-HSA system</div>

</li>

<div class="gallerytext">Steps performed when offloading calculations to the GPU on a HSA system, using the HSA functionality</div>

</li>

</ul></div></div></div>

Modern GPUs are very well suited to perform <a href="Single_instruction%2C_multiple_data" title="Single instruction, multiple data">single instruction, multiple data</a> (SIMD) and <a href="Single_instruction%2C_multiple_threads" title="Single instruction, multiple threads">single instruction, multiple threads</a> (SIMT), while modern CPUs are still being optimized for branching. etc.

<div class="mw-heading mw-heading2"><h2 id="Overview">Overview</h2></div>

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Originally introduced by <a href="Embedded_system" title="Embedded system">embedded systems</a> such as the <a href="Cell_Broadband_Engine" class="mw-redirect" title="Cell Broadband Engine">Cell Broadband Engine</a>, sharing system memory directly between multiple system actors makes heterogeneous computing more mainstream. Heterogeneous computing itself refers to systems that contain multiple processing units – <a href="Central_processing_unit" title="Central processing unit">central processing units</a> (CPUs), <a href="Graphics_processing_unit" title="Graphics processing unit">graphics processing units</a> (GPUs), <a href="Digital_signal_processor" title="Digital signal processor">digital signal processors</a> (DSPs), or any type of <a href="Application-specific_integrated_circuit" title="Application-specific integrated circuit">application-specific integrated circuits</a> (ASICs). The system architecture allows any accelerator, for instance a <a href="GPU" class="mw-redirect" title="GPU">graphics processor</a>, to operate at the same processing level as the system's CPU.

Among its main features, HSA defines a unified <a href="Virtual_address_space" title="Virtual address space">virtual address space</a> for compute devices: where GPUs traditionally have their own memory, separate from the main (CPU) memory, HSA requires these devices to share <a href="Page_(computer_memory)" title="Page (computer memory)">page tables</a> so that devices can exchange data by sharing <a href="Pointer_(computer_programming)" title="Pointer (computer programming)">pointers</a>. This is to be supported by custom <a href="Memory_management_unit" title="Memory management unit">memory management units</a>.<a href="#cite_note-whitepaper-2">[2]</a>: 6–7 To render interoperability possible and also to ease various aspects of programming, HSA is intended to be <a href="Instruction_set" class="mw-redirect" title="Instruction set">ISA</a>-agnostic for both CPUs and accelerators, and to support high-level programming languages.

So far, the HSA specifications cover:

<div class="mw-heading mw-heading3"><h3 id="HSA_Intermediate_Layer">HSA Intermediate Layer</h3></div>

HSAIL (Heterogeneous System Architecture Intermediate Language), a <a href="P-code_machine" title="P-code machine">virtual instruction set</a> for parallel programs

<ul><li>similar to <a href="LLVM_Intermediate_Representation" class="mw-redirect" title="LLVM Intermediate Representation">LLVM Intermediate Representation</a> and <a href="Standard_Portable_Intermediate_Representation" title="Standard Portable Intermediate Representation">SPIR</a> (used by <a href="OpenCL" title="OpenCL">OpenCL</a> and <a href="Vulkan_(API)" class="mw-redirect" title="Vulkan (API)">Vulkan</a>)</li>

<li>finalized to a specific instruction set by a <a href="Just-in-time_compilation" title="Just-in-time compilation">JIT compiler</a></li>

<li>make late decisions on which core(s) should run a task</li>

<li>explicitly parallel</li>

<li>supports exceptions, virtual functions and other high-level features</li>

<li>debugging support</li></ul>

<div class="mw-heading mw-heading3"><h3 id="HSA_memory_model">HSA memory model</h3></div>

<ul><li>compatible with <a href="C%2B%2B11" title="C++11">C++11</a>, OpenCL, <a href="Java_(programming_language)" title="Java (programming language)">Java</a> and <a href=".NET_Framework" title=".NET Framework">.NET</a> memory models</li>

<li>relaxed consistency</li>

<li>designed to support both managed languages (e.g. Java) and unmanaged languages (e.g. <a href="C_(programming_language)" title="C (programming language)">C</a>)</li>

<li>will make it much easier to develop 3rd-party compilers for a wide range of heterogeneous products programmed in <a href="Fortran" title="Fortran">Fortran</a>, C++, <a href="C%2B%2B_AMP" title="C++ AMP">C++ AMP</a>, Java, et al.</li></ul>

<div class="mw-heading mw-heading3"><h3 id="HSA_dispatcher_and_run-time">HSA dispatcher and run-time</h3></div>

<ul><li>designed to enable heterogeneous task queueing: a work queue per core, distribution of work into queues, load balancing by work stealing</li>

<li>any core can schedule work for any other, including itself</li>

<li>significant reduction of overhead of scheduling work for a core</li></ul>

Mobile devices are one of the HSA's application areas, in which it yields improved power efficiency.<a href="#cite_note-gpuscience-6">[6]</a>

<div class="mw-heading mw-heading3"><h3 id="Block_diagrams">Block diagrams</h3></div>

The illustrations below compare CPU-GPU coordination under HSA versus under traditional architectures.

<div class="gallerytext">Standard architecture with a discrete <a href="Graphics_card" title="Graphics card">GPU</a> attached to the <a href="PCI_Express" title="PCI Express">PCI Express</a> bus. <a href="Zero-copy" title="Zero-copy">Zero-copy</a> between the GPU and CPU is not possible due to distinct physical memories.</div>

</li>

<div class="gallerytext">HSA brings unified virtual memory and facilitates passing pointers over PCI Express instead of copying the entire data.</div>

</li>

<div class="gallerytext">In partitioned main memory, one part of the system memory is exclusively allocated to the GPU. As a result, zero-copy operation is not possible.</div>

</li>

<div class="gallerytext">Unified main memory, where GPU and CPU are HSA-enabled. This makes zero-copy operation possible.<a href="#cite_note-8">[8]</a></div>

</li>

<div class="gallerytext">The CPU's <a href="Memory_management_unit" title="Memory management unit">MMU</a> and the GPU's <a href="IOMMU" class="mw-redirect" title="IOMMU">IOMMU</a> must both comply with HSA hardware specifications.</div>

</li>

</ul></div></div></div>

<div class="mw-heading mw-heading2"><h2 id="Software_support">Software support</h2></div>

Some of the HSA-specific features implemented in the hardware need to be supported by the <a href="Operating_system_kernel" class="mw-redirect" title="Operating system kernel">operating system kernel</a> and specific device drivers. For example, support for AMD <a href="Radeon" title="Radeon">Radeon</a> and <a href="AMD_FirePro" title="AMD FirePro">AMD FirePro</a> graphics cards, and <a href="AMD_Accelerated_Processing_Unit" class="mw-redirect" title="AMD Accelerated Processing Unit">APUs</a> based on <a href="Graphics_Core_Next" title="Graphics Core Next">Graphics Core Next</a> (GCN), was merged into version 3.19 of the <a href="Linux_kernel_mainline" class="mw-redirect" title="Linux kernel mainline">Linux kernel mainline</a>, released on 8 February 2015.<a href="#cite_note-kernelnewbies-3.19-10">[10]</a> Programs do not interact directly with amdkfd, but queue their jobs utilizing the HSA runtime.<a href="#cite_note-11">[11]</a> This very first implementation, known as amdkfd, focuses on <a href="AMD_Accelerated_Processing_Unit" class="mw-redirect" title="AMD Accelerated Processing Unit">"Kaveri"</a> or "Berlin" APUs and works alongside the existing Radeon kernel graphics driver.

Additionally, amdkfd supports heterogeneous queuing (HQ), which aims to simplify the distribution of computational jobs among multiple CPUs and GPUs from the programmer's perspective. Support for heterogeneous memory management (HMM), suited only for graphics hardware featuring version 2 of the AMD's <a href="IOMMU" class="mw-redirect" title="IOMMU">IOMMU</a>, was accepted into the Linux kernel mainline version 4.14.<a href="#cite_note-12">[12]</a>

Integrated support for HSA platforms has been announced for the "Sumatra" release of <a href="OpenJDK" title="OpenJDK">OpenJDK</a>, due in 2015.<a href="#cite_note-13">[13]</a>

<a href="AMD_APP_SDK" title="AMD APP SDK">AMD APP SDK</a> is AMD's proprietary software development kit targeting <a href="Parallel_computing" title="Parallel computing">parallel computing</a>, available for Microsoft Windows and Linux. Bolt is a C++ template library optimized for heterogeneous computing.<a href="#cite_note-14">[14]</a>

<a href="GPUOpen" title="GPUOpen">GPUOpen</a> comprehends a couple of other software tools related to HSA. <a href="CodeXL" title="CodeXL">CodeXL</a> version 2.0 includes an HSA profiler.<a href="#cite_note-15">[15]</a>

<div class="mw-heading mw-heading2"><h2 id="Hardware_support">Hardware support</h2></div>

As of February 2015, only AMD's "Kaveri" A-series APUs (cf. <a href="List_of_AMD_Accelerated_Processing_Unit_microprocessors" class="mw-redirect" title="List of AMD Accelerated Processing Unit microprocessors">"Kaveri" desktop processors</a> and <a href="List_of_AMD_Accelerated_Processing_Unit_microprocessors" class="mw-redirect" title="List of AMD Accelerated Processing Unit microprocessors">"Kaveri" mobile processors</a>) and Sony's <a href="PlayStation_4" title="PlayStation 4">PlayStation 4</a> allowed the <a href="Graphics_processing_unit#Integrated_graphics" title="Graphics processing unit">integrated GPU</a> to access memory via version 2 of the AMD's IOMMU. Earlier APUs (Trinity and Richland) included the version 2 IOMMU functionality, but only for use by an external GPU connected via PCI Express.

Post-2015 Carrizo and Bristol Ridge APUs also include the version 2 IOMMU functionality for the integrated GPU.

The following table shows features of <a href="AMD" title="AMD">AMD</a>'s processors with 3D graphics, including <a href="AMD_APU" title="AMD APU">APUs</a> (see also: <a href="List_of_AMD_processors_with_3D_graphics" title="List of AMD processors with 3D graphics">List of AMD processors with 3D graphics</a>).

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<th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Platform

</th>

<th colspan="14">High, standard and low power

</th>

<th colspan="9">Low and ultra-low power

</th></tr>

<tr>

<th rowspan="11" style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Codename</th>

<th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" rowspan="2">Server

</th>

<th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Basic

</th>

</th>

<th><a href="List_of_AMD_processors_with_3D_graphics#Opteron_X3000-series_"Toronto"_(2017)" title="List of AMD processors with 3D graphics">Toronto</a>

</th>

</th>

</th></tr>

<tr>

<th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Micro

</th>

</th>

<th>

</th>

<th><a href="List_of_AMD_processors_with_3D_graphics#Opteron_X2100-series_"Kyoto"_(2013)" title="List of AMD processors with 3D graphics">Kyoto</a>

</th>

</th></tr>

<tr>

<th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" rowspan="4">Desktop

</th>

<th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Performance

</th>

</th>

<th rowspan="2"><a href="List_of_AMD_processors_with_3D_graphics#"Raphael"_(2022)" title="List of AMD processors with 3D graphics">Raphael</a>

</th>

<th rowspan="3"><a href="List_of_AMD_processors_with_3D_graphics#"Phoenix"_(2024)" title="List of AMD processors with 3D graphics">Phoenix</a>

</th>

</th></tr>

<tr>

<th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Mainstream

</th>

<th rowspan="2"><a href="List_of_AMD_processors_with_3D_graphics#Lynx:_"Llano"_(2011)" title="List of AMD processors with 3D graphics">Llano</a>

</th>

<th rowspan="2"><a href="List_of_AMD_processors_with_3D_graphics#Virgo:_"Trinity"_(2012)" title="List of AMD processors with 3D graphics">Trinity</a>

</th>

<th rowspan="2"><a href="List_of_AMD_processors_with_3D_graphics#"Richland"_(2013)" title="List of AMD processors with 3D graphics">Richland</a>

</th>

<th rowspan="2"><a href="List_of_AMD_processors_with_3D_graphics#"Kaveri"_(2014)" title="List of AMD processors with 3D graphics">Kaveri</a>

</th>

<th rowspan="2"><a href="Steamroller_(microarchitecture)" title="Steamroller (microarchitecture)">Kaveri Refresh (Godavari)</a>

</th>

<th rowspan="2"><a href="List_of_AMD_processors_with_3D_graphics#"Carrizo"_(2016)" title="List of AMD processors with 3D graphics">Carrizo</a>

</th>

<th rowspan="2"><a href="List_of_AMD_processors_with_3D_graphics#"Bristol_Ridge"_(2016)" title="List of AMD processors with 3D graphics">Bristol Ridge</a>

</th>

<th rowspan="2"><a href="List_of_AMD_processors_with_3D_graphics#"Raven_Ridge"_(2018)" title="List of AMD processors with 3D graphics">Raven Ridge</a>

</th>

<th rowspan="2"><a href="List_of_AMD_processors_with_3D_graphics#"Picasso"_(2019)" title="List of AMD processors with 3D graphics">Picasso</a>

</th>

<th rowspan="2"><a href="List_of_AMD_processors_with_3D_graphics#"Renoir"_(2020)" title="List of AMD processors with 3D graphics">Renoir</a>

</th>

<th rowspan="2"><a href="List_of_AMD_processors_with_3D_graphics#"Cezanne"_(2021)" title="List of AMD processors with 3D graphics">Cezanne</a>

</th>

<th>

</th></tr>

<tr>

<th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Entry

</th>

</th></tr>

<tr>

<th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Basic

</th>

</th>

<th>

</th>

<th><a href="List_of_AMD_processors_with_3D_graphics#"Kabini"_(2013,_SoC)" title="List of AMD processors with 3D graphics">Kabini</a>

</th>

</th>

</th>

</th></tr>

<tr>

<th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" rowspan="4">Mobile</th>

<th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Performance

</th>

</th>

<th><a href="List_of_AMD_processors_with_3D_graphics#H" title="List of AMD processors with 3D graphics">Renoir</a>

</th>

<th><a href="List_of_AMD_processors_with_3D_graphics#H_2" title="List of AMD processors with 3D graphics">Cezanne</a>

</th>

<th rowspan="2"><a href="List_of_AMD_processors_with_3D_graphics#"Rembrandt"_(2022)" title="List of AMD processors with 3D graphics">Rembrandt</a>

</th>

<th rowspan="2"><a href="List_of_AMD_processors_with_3D_graphics#"Dragon_Range"_(2023)" title="List of AMD processors with 3D graphics">Dragon Range</a>

</th>

<th>

</th>

</th></tr>

<tr>

<th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Mainstream

</th>

<th rowspan="2"><a href="List_of_AMD_processors_with_3D_graphics#Sabine:_"Llano"_(2011)" title="List of AMD processors with 3D graphics">Llano</a>

</th>

<th rowspan="2"><a href="List_of_AMD_processors_with_3D_graphics#Comal:_"Trinity"_(2012)" title="List of AMD processors with 3D graphics">Trinity</a>

</th>

<th rowspan="2"><a href="List_of_AMD_processors_with_3D_graphics#"Richland"_(2013)_2" title="List of AMD processors with 3D graphics">Richland</a>

</th>

<th rowspan="2"><a href="List_of_AMD_processors_with_3D_graphics#"Kaveri"_(2014)_2" title="List of AMD processors with 3D graphics">Kaveri</a>

</th>

</th>

<th rowspan="2"><a href="List_of_AMD_processors_with_3D_graphics#"Carrizo"_(2015)" title="List of AMD processors with 3D graphics">Carrizo</a>

</th>

<th rowspan="2"><a href="List_of_AMD_processors_with_3D_graphics#"Bristol_Ridge"_(2016)_2" title="List of AMD processors with 3D graphics">Bristol Ridge</a>

</th>

<th rowspan="2"><a href="List_of_AMD_processors_with_3D_graphics#"Raven_Ridge"_(2017)" title="List of AMD processors with 3D graphics">Raven Ridge</a>

</th>

<th><a href="List_of_AMD_processors_with_3D_graphics#"Picasso"_(2019)_2" title="List of AMD processors with 3D graphics">Picasso</a>

</th>

<th><a href="List_of_AMD_processors_with_3D_graphics#U" title="List of AMD processors with 3D graphics">Renoir</a> <a href="List_of_AMD_processors_with_3D_graphics#"Lucienne"_(2021)" title="List of AMD processors with 3D graphics">Lucienne</a>

</th>

<th><a href="List_of_AMD_processors_with_3D_graphics#U_2" title="List of AMD processors with 3D graphics">Cezanne</a> <a href="List_of_AMD_processors_with_3D_graphics#"Barceló"_(2022)" title="List of AMD processors with 3D graphics">Barceló</a>

</th>

<th><a href="List_of_AMD_processors_with_3D_graphics#"Phoenix"_(2023)" title="List of AMD processors with 3D graphics">Phoenix</a>

</th></tr>

<tr>

<th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Entry

</th>

</th>

</th>

</th>

</th>

<th rowspan="2"><a href="List_of_AMD_processors_with_3D_graphics#"Mendocino"_(2022)" title="List of AMD processors with 3D graphics">Mendocino</a>

</th></tr>

<tr>

<th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Basic

</th>

</th>

<th><a href="List_of_AMD_processors_with_3D_graphics#Brazos:_"Desna",_"Ontario",_"Zacate"_(2011)" title="List of AMD processors with 3D graphics">Desna, Ontario, Zacate</a>

</th>

<th><a href="List_of_AMD_processors_with_3D_graphics#"Kabini",_"Temash"_(2013)" title="List of AMD processors with 3D graphics">Kabini, Temash</a>

</th>

<th><a href="List_of_AMD_processors_with_3D_graphics#"Beema",_"Mullins"_(2014)" title="List of AMD processors with 3D graphics">Beema, Mullins</a>

</th>

<th><a href="List_of_AMD_processors_with_3D_graphics#"Carrizo-L"_(2015)" title="List of AMD processors with 3D graphics">Carrizo-L</a>

</th>

<th><a href="List_of_AMD_processors_with_3D_graphics#"Stoney_Ridge"_(2016)" title="List of AMD processors with 3D graphics">Stoney Ridge</a>

</th>

<th><a href="List_of_AMD_processors_with_3D_graphics#"Pollock"_(2020)" title="List of AMD processors with 3D graphics">Pollock</a>

</th>

<th>

</th></tr>

<tr>

<th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="2">Embedded

</th>

<th>

</th>

<th><a href="List_of_AMD_processors_with_3D_graphics#Comal:_"Trinity"_(2012)_2" title="List of AMD processors with 3D graphics">Trinity</a>

</th>

<th>

</th>

<th><a href="List_of_AMD_processors_with_3D_graphics#"Bald_Eagle"_(2014)" title="List of AMD processors with 3D graphics">Bald Eagle</a>

</th>

<th>

</th>

<th><a href="List_of_AMD_processors_with_3D_graphics#"Merlin_Falcon"_(2015,_SoC)" title="List of AMD processors with 3D graphics">Merlin Falcon</a>, <a href="List_of_AMD_processors_with_3D_graphics#I-Family:_"Brown_Falcon"_(2016,_SoC)" title="List of AMD processors with 3D graphics">Brown Falcon</a>

</th>

<th>

</th>

<th><a href="List_of_AMD_processors_with_3D_graphics#V1000-Family:_"Great_Horned_Owl"_(2018,_SoC)" title="List of AMD processors with 3D graphics">Great Horned Owl</a>

</th>

<th>

</th>

</th>

</th>

<th><a href="List_of_AMD_processors_with_3D_graphics#Brazos:_"Ontario"_and_"Zacate"_(2011)" title="List of AMD processors with 3D graphics">Ontario, Zacate</a>

</th>

<th><a href="List_of_AMD_processors_with_3D_graphics#"Kabini"_(2013,_SoC)_2" title="List of AMD processors with 3D graphics">Kabini</a>

</th>

<th><a href="List_of_AMD_processors_with_3D_graphics#"Steppe_Eagle"_(2014,_SoC)" title="List of AMD processors with 3D graphics">Steppe Eagle</a>, <a href="List_of_AMD_processors_with_3D_graphics#"Crowned_Eagle"_(2014,_SoC)" title="List of AMD processors with 3D graphics">Crowned Eagle</a>, <a href="List_of_AMD_processors_with_3D_graphics#LX-Family_(2016,_SoC)" title="List of AMD processors with 3D graphics">LX-Family</a>

</th>

<th>

</th>

<th><a href="List_of_AMD_processors_with_3D_graphics#J-Family:_"Prairie_Falcon"_(2016,_SoC)" title="List of AMD processors with 3D graphics">Prairie Falcon</a>

</th>

<th><a href="List_of_AMD_processors_with_3D_graphics#R1000-Family:_"Banded_Kestrel"_(2019,_SoC)" title="List of AMD processors with 3D graphics">Banded Kestrel</a>

</th>

<th>

</th>

<th><a href="List_of_AMD_processors_with_3D_graphics#R2000-Family:_"River_Hawk"_(2022,_SoC)" title="List of AMD processors with 3D graphics">River Hawk</a>

</th>

<th>

</th></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Released</td>

<td>Jan 2014

</td>

<td>Mar 2020

</td>

<td>Nov 2022

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">CPU <a href="Microarchitecture" title="Microarchitecture">microarchitecture</a>

</td>

</td>

<td colspan="2"><a href="Piledriver_(microarchitecture)" title="Piledriver (microarchitecture)">Piledriver</a>

</td>

<td colspan="2"><a href="Steamroller_(microarchitecture)" title="Steamroller (microarchitecture)">Steamroller</a>

</td>

<td><a href="Excavator_(microarchitecture)" title="Excavator (microarchitecture)">Excavator</a>

</td>

<td>"<a href="Excavator_(microarchitecture)" title="Excavator (microarchitecture)">Excavator+</a>"<a href="#cite_note-16">[16]</a>

</td>

</td>

</td>

</td>

</td>

</td>

</td>

<td><a href="Bobcat_(microarchitecture)" title="Bobcat (microarchitecture)">Bobcat</a>

</td>

<td><a href="Jaguar_(microarchitecture)" title="Jaguar (microarchitecture)">Jaguar</a>

</td>

</td>

</td>

<td>"<a href="Excavator_(microarchitecture)" title="Excavator (microarchitecture)">Excavator+</a>"

</td>

</td>

</td>

<td>"<a href="Zen_2" title="Zen 2">Zen 2+</a>"

</td></tr>

<tr>

<td colspan="5"><a href="X86-64" title="X86-64">x86-64</a> v3

</td></tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" rowspan="5">Socket

</td>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" rowspan="4">Desktop

</td>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Performance

</td>

<td colspan="12" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—

</td>

</td>

<td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—

</td>

<td rowspan="3" colspan="9" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Mainstream

</td>

<td colspan="5" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—

</td>

</td>

<td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—

</td>

<th data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—

</th></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Entry

</td>

</td>

</td>

</td>

</td>

</td>

<td colspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Basic

</td>

<td colspan="14" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—

</td>

<td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—

</td>

</td>

<td>FP5

</td>

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="2">Other

</td>

</td>

</td>

</td>

<td colspan="2">FP4

</td>

<td colspan="2">FP5

</td>

<td colspan="2">FP6

</td>

<td>FP7

</td>

<td>FL1

</td>

<td>FP7 FP7r2 FP8

</td>

</td>

</td>

</td>

<td>FP4

</td>

<td>FP5

</td>

<td>FT5

</td>

<td>FP5

</td>

<td>FT6

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="PCI_Express" title="PCI Express">PCI Express</a> version

</td>

<td colspan="3">2.0

</td>

<td colspan="8">3.0

</td>

<td>4.0

</td>

<td>5.0

</td>

<td>4.0

</td>

<td colspan="4">2.0

</td>

<td colspan="5">3.0

</td></tr>

<tr>

</td>

<td colspan="9" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—

</td></tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fab.</a> (<a href="Nanometre" title="Nanometre">nm</a>)

</td>

<td colspan="3"><a href="GlobalFoundries" title="GlobalFoundries">GF</a> <a href="32_nm_process" title="32 nm process">32SHP</a> (<a href="HKMG" class="mw-redirect" title="HKMG">HKMG</a> <a href="Silicon_on_insulator" title="Silicon on insulator">SOI</a>)

</td>

<td colspan="4">GF <a href="32_nm_process" title="32 nm process">28SHP</a> (HKMG bulk)

</td>

<td>GF <a href="14_nm_process" title="14 nm process">14LPP</a> (<a href="FinFET" class="mw-redirect" title="FinFET">FinFET</a> bulk)

</td>

<td>GF <a href="14_nm_process" title="14 nm process">12LP</a> (FinFET bulk)

</td>

<td colspan="2"><a href="TSMC" title="TSMC">TSMC</a> <a href="7_nm_process" title="7 nm process">N7</a> (FinFET bulk)

</td>

<td>TSMC <a href="7_nm_process" title="7 nm process">N6</a> (FinFET bulk)

</td>

<td>CCD: TSMC <a href="5_nm_process" title="5 nm process">N5</a> (FinFET bulk) cIOD: TSMC <a href="7_nm_process" title="7 nm process">N6</a> (FinFET bulk)

</td>

<td>TSMC <a href="5_nm_process" title="5 nm process">4nm</a> (FinFET bulk)

</td>

<td>TSMC <a href="45_nm_process" title="45 nm process">N40</a> (bulk)

</td>

<td>TSMC <a href="32_nm_process" title="32 nm process">N28</a> (HKMG bulk)

</td>

<td colspan="3">GF 28SHP (HKMG bulk)

</td>

<td colspan="2">GF <a href="14_nm_process" title="14 nm process">14LPP</a> (<a href="FinFET" class="mw-redirect" title="FinFET">FinFET</a> bulk)

</td>

<td>GF <a href="14_nm_process" title="14 nm process">12LP</a> (FinFET bulk)

</td>

<td>TSMC <a href="7_nm_process" title="7 nm process">N6</a> (FinFET bulk)

</td></tr>

<tr>

<td>156

</td>

<td>CCD: (2x) 70 cIOD: 122

</td>

<td>~100

</td></tr>

<tr>

<td>8

</td></tr>

<tr>

<td>15

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max stock APU base clock (GHz)</td>

<td>2.8

</td></tr>

<tr>

<td colspan="9">1

</td></tr>

<tr>

<td colspan="9">1

</td></tr>

<tr>

<td colspan="9">1

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max cores per CCX</td>

<td colspan="2">4

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max <a href="Central_processing_unit" title="Central processing unit">CPU</a><a href="#cite_note-apudef-21">[c]</a> <a href="Multi-core_processor" title="Multi-core processor">cores</a> per APU</td>

<td colspan="2">4

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max <a href="Thread_(computing)" title="Thread (computing)">threads</a> per CPU core</td>

<td colspan="4">2

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Integer pipeline structure</td>

<td>4+2+1

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">i386, i486, i586, CMOV, NOPL, i686, <a href="Physical_Address_Extension" title="Physical Address Extension">PAE</a>, <a href="NX_bit" title="NX bit">NX bit</a>, CMPXCHG16B, <a href="AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="Second_Level_Address_Translation#RVI" title="Second Level Address Translation">RVI</a>, <a href="Bit_Manipulation_Instruction_Sets" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, and 64-bit LAHF/SAHF</td>

</td>

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="IOMMU" class="mw-redirect" title="IOMMU">IOMMU</a><a href="#cite_note-iommubios-22">[d]</a></td>

<td colspan="7">v2

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="Bit_Manipulation_Instruction_Sets" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="AES_instruction_set" title="AES instruction set">AES-NI</a>, <a href="CLMUL" class="mw-redirect" title="CLMUL">CLMUL</a>, and <a href="F16C" title="F16C">F16C</a>

</td>

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">MOVBE</td>

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="X86_virtualization#Interrupt_virtualization_(AMD_AVIC_and_Intel_APICv)" title="X86 virtualization">AVIC</a>, <a href="Bit_Manipulation_Instruction_Sets" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI2</a>, <a href="RDRAND" title="RDRAND">RDRAND</a>, and MWAITX/MONITORX

</td>

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">SME<a href="#cite_note-firmware-23">[e]</a>, TSME<a href="#cite_note-firmware-23">[e]</a>, <a href="Intel_ADX" title="Intel ADX">ADX</a>, <a href="Intel_SHA_extensions" class="mw-redirect" title="Intel SHA extensions">SHA</a>, <a href="RDSEED" class="mw-redirect" title="RDSEED">RDSEED</a>, <a href="Supervisor_Mode_Access_Prevention" title="Supervisor Mode Access Prevention">SMAP</a>, <a href="Control_register#SMEP" title="Control register">SMEP</a>, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing</td>

</td>

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="Second_Level_Address_Translation#Mode_Based_Execution_Control" title="Second Level Address Translation">GMET</a>, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT</td>

</td>

</td></tr>

<tr>

</td>

</td></tr>

<tr>

</td></tr>

<td colspan="4">1

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Pipes per FPU</td>

<td colspan="9">2

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">FPU pipe width</td>

<td>256-bit

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">CPU <a href="Instruction_set" class="mw-redirect" title="Instruction set">instruction set</a> <a href="Single_instruction%2C_multiple_data" title="Single instruction, multiple data">SIMD</a> level</td>

</td>

</td></tr>

<tr>

<td colspan="13" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—

</td>

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="PREFETCHW" class="mw-redirect" title="PREFETCHW">PREFETCH/PREFETCHW</a></td>

</td>

</td></tr>

<tr>

</td>

<td rowspan="2" colspan="9" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—

</td></tr>

<tr>

</td></tr>

<tr>

</td>

</td></tr>

<tr>

</td>

</td></tr>

</td>

</td></tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="L1_cache" class="mw-redirect" title="L1 cache">L1</a> data cache per core (KiB)</td>

<td colspan="9">32

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">L1 data cache <a href="Cache_placement_policies#Set-associative_cache" title="Cache placement policies">associativity</a> (ways)</td>

<td colspan="9">8

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">L1 instruction caches per <a href="Multi-core_processor" title="Multi-core processor">core</a></td>

<td colspan="7">1

</td>

<td colspan="4">1

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max APU total L1 instruction cache (KiB)</td>

<td>256

</td>

<td colspan="2">128

</td>

<td>96

</td>

<td colspan="4">128

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">L1 instruction cache <a href="Cache_placement_policies#Set-associative_cache" title="Cache placement policies">associativity</a> (ways)</td>

<td colspan="5">8

</td>

<td colspan="4">2

</td>

<td>3

</td>

<td colspan="3">4

</td>

<td>8

</td></tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="L2_cache" class="mw-redirect" title="L2 cache">L2 caches</a> per <a href="Multi-core_processor" title="Multi-core processor">core</a></td>

<td colspan="4">1

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max APU total L2 cache (MiB)</td>

<td colspan="2">2

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">L2 cache <a href="Cache_placement_policies#Set-associative_cache" title="Cache placement policies">associativity</a> (ways)</td>

<td colspan="4">8

</td></tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max on-die <a href="L3_cache" class="mw-redirect" title="L3 cache">L3 cache</a> per CCX (MiB)</td>

<td colspan="4">4

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max 3D V-Cache per CCD (MiB)</td>

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max total in-CCD <a href="L3_cache" class="mw-redirect" title="L3 cache">L3 cache</a> per APU (MiB)</td>

<td colspan="4">4

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max. total 3D V-Cache per APU (MiB)</td>

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max. board <a href="L3_cache" class="mw-redirect" title="L3 cache">L3 cache</a> per APU (MiB)</td>

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max total <a href="L3_cache" class="mw-redirect" title="L3 cache">L3 cache</a> per APU (MiB)</td>

<td colspan="4">4

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">APU L3 cache <a href="Cache_placement_policies#Set-associative_cache" title="Cache placement policies">associativity</a> (ways)</td>

<td colspan="4">16

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">L3 cache scheme</td>

<td colspan="7"><a href="Victim_cache" title="Victim cache">Victim</a></td>

<td colspan="4"><a href="Victim_cache" title="Victim cache">Victim</a>

</td></tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max. <a href="L4_cache" class="mw-redirect" title="L4 cache">L4 cache</a></td>

</td></tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max stock <a href="Dynamic_random-access_memory" title="Dynamic random-access memory">DRAM</a> support</td>

<td colspan="2">DDR4-3200, <a href="LPDDR#LPDDR4" title="LPDDR">LPDDR4</a>-4266</td>

<td><a href="DDR5_SDRAM" title="DDR5 SDRAM">DDR5</a>-4800, <a href="LPDDR#LPDDR5" title="LPDDR">LPDDR5</a>-6400</td>

<td><a href="DDR5_SDRAM" title="DDR5 SDRAM">DDR5</a>-5600, <a href="LPDDR#LPDDR5x" title="LPDDR">LPDDR5x</a>-7500</td>

<td>LPDDR5-5500

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max <a href="Dynamic_random-access_memory" title="Dynamic random-access memory">DRAM</a> channels per APU</td>

<td colspan="2">2

</td></tr>

<tr>

<td>120.000

</td>

<td>88.000

</td></tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">GPU <a href="Microarchitecture" title="Microarchitecture">microarchitecture</a></td>

<td><a href="TeraScale_(microarchitecture)#TeraScale_2_"Evergreen"-family" title="TeraScale (microarchitecture)">TeraScale 2 (VLIW5)</a></td>

<td colspan="2"><a href="TeraScale_(microarchitecture)#TeraScale_3_"Northern_Islands"-family" title="TeraScale (microarchitecture)">TeraScale 3 (VLIW4)</a></td>

<td><a href="TeraScale_(microarchitecture)#TeraScale_2_"Evergreen"-family" title="TeraScale (microarchitecture)">TeraScale 2 (VLIW5)</a></td>

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">GPU <a href="Instruction_set" class="mw-redirect" title="Instruction set">instruction set</a></td>

<td colspan="3"><a href="TeraScale_(microarchitecture)" title="TeraScale (microarchitecture)">TeraScale</a> instruction set</td>

<td colspan="8"><a href="Graphics_Core_Next#Instruction_set" title="Graphics Core Next">GCN instruction set</a></td>

<td colspan="3"><a href="RDNA_(microarchitecture)#Instruction_set" title="RDNA (microarchitecture)">RDNA instruction set</a></td>

<td><a href="TeraScale_(microarchitecture)" title="TeraScale (microarchitecture)">TeraScale</a> instruction set</td>

<td colspan="7"><a href="Graphics_Core_Next#Instruction_set" title="Graphics Core Next">GCN instruction set</a></td>

<td><a href="RDNA_(microarchitecture)#Instruction_set" title="RDNA (microarchitecture)">RDNA instruction set</a>

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max stock GPU base clock (MHz)</td>

<td>

</td>

<td>1900

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max stock GPU base <a href="GFLOPS" class="mw-redirect" title="GFLOPS">GFLOPS</a><a href="#cite_note-SFLOPS-26">[g]</a></td>

<td>

</td>

<td>486.4

</td></tr>

<td rowspan="2" style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">3D engine<a href="#cite_note-27">[h]</a></td>

<td>128:?:?

</td></tr>

<tr>

<td colspan="3">IOMMUv1</td>

<td colspan="11"><a href="Heterogeneous_Memory_Management" class="mw-redirect" title="Heterogeneous Memory Management">IOMMUv2</a></td>

<td colspan="2">IOMMUv1</td>

<td colspan="5">IOMMUv2

</td></tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Video decoder</td>

</td>

<td rowspan="2">VCN 3.1

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Video encoder</td>

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">AMD Fluid Motion

</td>

</td>

</td>

</td>

</td>

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">GPU power saving</td>

<td><a href="AMD_PowerPlay" title="AMD PowerPlay">PowerPlay</a></td>

<td colspan="13"><a href="AMD_PowerTune" title="AMD PowerTune">PowerTune</a></td>

<td><a href="AMD_PowerPlay" title="AMD PowerPlay">PowerPlay</a></td>

<td colspan="8"><a href="AMD_PowerTune" title="AMD PowerTune">PowerTune</a><a href="#cite_note-31">[23]</a>

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="AMD_TrueAudio" title="AMD TrueAudio">TrueAudio</a></td>

<td colspan="4" style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">?

</td>

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="FreeSync" class="mw-redirect" title="FreeSync">FreeSync</a></td>

<td colspan="11" style="background:#DFD">1 2

</td>

<td colspan="88" style="background:#DFD">1 2

</td></tr>

<tr>

<td>2.3

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="PlayReady" title="PlayReady">PlayReady</a><a href="#cite_note-DRM-33">[i]</a></td>

<td colspan="4">3.0 not yet

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="AMD_Eyefinity" title="AMD Eyefinity">Supported displays</a><a href="#cite_note-35">[j]</a></td>

<td colspan="2">3 (desktop) 4 (mobile, embedded)</td>

<td colspan="2">4

</td></tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><code>/drm/radeon</code><a href="#cite_note-drm-36">[k]</a><a href="#cite_note-37">[26]</a><a href="#cite_note-Radeon_Feature_Matrix-38">[27]</a></td>

</td>

</td></tr>

<tr>

<td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><code>/drm/amdgpu</code><a href="#cite_note-drm-36">[k]</a><a href="#cite_note-39">[28]</a></td>

</td>

</td></tr></tbody></table>

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<li id="cite_note-18"><a href="#cite_ref-18">^</a> For FM2+ Excavator models: A8-7680, A6-7480 & Athlon X4 845.

</li>

<li id="cite_note-nodedef-20"><a href="#cite_ref-nodedef_20-0">^</a> A PC would be one node.

</li>

<li id="cite_note-apudef-21"><a href="#cite_ref-apudef_21-0">^</a> An APU combines a CPU and a GPU. Both have cores.

</li>

<li id="cite_note-iommubios-22"><a href="#cite_ref-iommubios_22-0">^</a> Requires firmware support.

</li>

<li id="cite_note-firmware-23">^ <a href="#cite_ref-firmware_23-0">a</a> <a href="#cite_ref-firmware_23-1">b</a> Requires firmware support.

</li>

<li id="cite_note-sse4a-24"><a href="#cite_ref-sse4a_24-0">^</a> No SSE4. No SSSE3.

</li>

<li id="cite_note-SFLOPS-26"><a href="#cite_ref-SFLOPS_26-0">^</a> <a href="Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation.

</li>

<li id="cite_note-27"><a href="#cite_ref-27">^</a> <a href="Unified_shader_model" title="Unified shader model">Unified shaders</a> : <a href="Texture_mapping_unit" title="Texture mapping unit">texture mapping units</a> : <a href="Render_output_unit" title="Render output unit">render output units</a>

</li>

<li id="cite_note-DRM-33">^ <a href="#cite_ref-DRM_33-0">a</a> <a href="#cite_ref-DRM_33-1">b</a> To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.

</li>

<li id="cite_note-35"><a href="#cite_ref-35">^</a> To feed more than two displays, the additional panels must have native <a href="DisplayPort" title="DisplayPort">DisplayPort</a> support.<a href="#cite_note-34">[25]</a> Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.

</li>

<li id="cite_note-drm-36">^ <a href="#cite_ref-drm_36-0">a</a> <a href="#cite_ref-drm_36-1">b</a> DRM (<a href="Direct_Rendering_Manager" title="Direct Rendering Manager">Direct Rendering Manager</a>) is a component of the Linux kernel. Support in this table refers to the most current version.

</li>

</ol></div></div>

ARM's <a href="Bifrost_(microarchitecture)" class="mw-redirect" title="Bifrost (microarchitecture)">Bifrost</a> microarchitecture, as implemented in the Mali-G71,<a href="#cite_note-41">[30]</a> is fully compliant with the HSA 1.1 hardware specifications. As of June 2016, ARM has not announced software support that would use this hardware feature.

<ul><li><a href="General-purpose_computing_on_graphics_processing_units" class="mw-disambig" title="General-purpose computing on graphics processing units">General-purpose computing on graphics processing units</a> (GPGPU)</li>

<li><a href="Non-Uniform_Memory_Access" class="mw-redirect" title="Non-Uniform Memory Access">Non-Uniform Memory Access</a> (NUMA)</li>

<li><a href="OpenMP" title="OpenMP">OpenMP</a></li>

<li><a href="Shared_memory" title="Shared memory">Shared memory</a></li>

<li>A technique enabling zero-copy operation for a CPU and a parallel accelerator <a href="#cite_note-42">[31]</a></li></ul>

<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>

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</li>

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<li id="cite_note-4"><a href="#cite_ref-4">^</a> <cite id="CITEREFJoel_Hruska2013" class="citation web cs1">Joel Hruska (26 August 2013). <a rel="nofollow" class="external text" href="http://www.extremetech.com/gaming/164817-setting-hsail-amd-cpu-gpu-cooperation">"Setting HSAIL: AMD explains the future of CPU/GPU cooperation"</a>. <a href="ExtremeTech" title="ExtremeTech">ExtremeTech</a>. <a href="Ziff_Davis" title="Ziff Davis">Ziff Davis</a>.</cite>

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<li id="cite_note-5"><a href="#cite_ref-5">^</a> <cite id="CITEREFLinaro2014" class="citation web cs1">Linaro (21 March 2014). <a rel="nofollow" class="external text" href="https://www.slideshare.net/mobile/linaroorg/hsa-linaro-updatejuly102013">"LCE13: Heterogeneous System Architecture (HSA) on ARM"</a>. slideshare.net.</cite>

</li>

<li id="cite_note-gpuscience-6">^ <a href="#cite_ref-gpuscience_6-0">a</a> <a href="#cite_ref-gpuscience_6-1">b</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140201183411/http://gpuscience.com/cs/heterogeneous-system-architecture-purpose-and-outlook/">"Heterogeneous System Architecture: Purpose and Outlook"</a>. gpuscience.com. 9 November 2012. Archived from <a rel="nofollow" class="external text" href="http://gpuscience.com/cs/heterogeneous-system-architecture-purpose-and-outlook/">the original</a> on 1 February 2014. Retrieved 24 May 2014.</cite>

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<li id="cite_note-7"><a href="#cite_ref-7">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://embedded-computing.com/articles/heterogeneous-processing-using-mix-cpu-gpu-elements/">"Heterogeneous system architecture: Multicore image processing using a mix of CPU and GPU elements"</a>. Embedded Computing Design. Retrieved 23 May 2014.</cite>

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<li id="cite_note-8"><a href="#cite_ref-8">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.semiaccurate.com/2014/01/15/technical-look-amds-kaveri-architecture/">"Kaveri microarchitecture"</a>. <a href="SemiAccurate" title="SemiAccurate">SemiAccurate</a>. 15 January 2014.</cite>

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<div class="side-box-text plainlist">Wikimedia Commons has media related to <a href="https://commons.wikimedia.org/wiki/Category:Heterogeneous_System_Architecture" class="extiw external" title="commons:Category:Heterogeneous System Architecture">Heterogeneous System Architecture</a>.</div></div>

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<ul><li><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=ln8JpfaLvbM">HSA Heterogeneous System Architecture Overview</a> on <a href="YouTube_video_(identifier)" class="mw-redirect" title="YouTube video (identifier)">YouTube</a> by Vinod Tipparaju at <a href="ACM/IEEE_Supercomputing_Conference" title="ACM/IEEE Supercomputing Conference">SC13</a> in November 2013</li>

<li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20160514070602/http://www.mpsoc-forum.org/previous/2013/slides/8-Hegde.pdf">HSA and the software ecosystem</a></li>

<li><a rel="nofollow" class="external text" href="http://www-conf.slac.stanford.edu/xldb2012/talks/xldb2012_wed_1400_MichaelHouston.pdf">2012 – HSA by Michael Houston</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20160305141652/http://www-conf.slac.stanford.edu/xldb2012/talks/xldb2012_wed_1400_MichaelHouston.pdf">Archived</a> 5 March 2016 at the <a href="Wayback_Machine" title="Wayback Machine">Wayback Machine</a></li></ul>

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